Intel’s 18A-P chip process enters risk production on schedule

Intel 18A-P Chip Process Enters Risk Production, Advancing Foundry Ambitions

Intel announced on Tuesday at the 2026 VLSI Symposium in Honolulu that its 18A-P process node has entered risk production on schedule, marking a milestone in the chipmaker’s effort to rebuild its contract manufacturing business and attract external customers.stocktitan

A Faster, Cooler Chip Node

The 18A-P is the first performance-enhanced variant in the Intel 18A family, which uses RibbonFET gate-all-around transistors and PowerVia backside power delivery. According to Intel, the node delivers 9% higher performance at the same power level, or 18% lower power consumption at equivalent performance, compared to the standard 18A process.moneycontrol

Intel also introduced Power Boost, a dual-contact, low-resistance transistor option designed to increase drive current and enable higher operating frequencies. The company reported thermal resistance improvements of 20% to 40% through material and design innovations, along with 10% to 30% better via resistance. The node is fully compatible with Intel 18A design rules, allowing customers to reuse existing intellectual property and design flows without modification.stocktitan

Courting External Foundry Clients

The milestone arrives as Intel works to land commitments from major chip designers for its foundry business. CEO Lip-Bu Tan said in May that Intel expects commitments from multiple foundry customers in the second half of 2026.cnbc

The most closely watched potential deal involves Apple. According to a May report from The Wall Street Journal, cited by CNBC, Apple and Intel have reached a preliminary agreement for Intel to manufacture certain chips for Apple devices using the 18A process family. Analyst Ming-Chi Kuo has forecast that Apple could use Intel Foundry for entry-level M-series chips, with shipments potentially beginning in 2027.yahoo

Long-Term Research Bets

Beyond 18A-P, Intel presented research at the symposium on technologies aimed at future scaling, including monolithic CFET inverters with vertically stacked devices at a 45nm gate pitch, 300mm integration of gallium nitride power devices with silicon logic, and subtractive ruthenium interconnects with airgap integration that achieved roughly 35% capacitance reduction versus copper.stocktitan